SMV Model Checking for FBDs
1. Verilog Translation from FBDs
- Automatically translate Synchronous Verilog programs from POSCON pSET FBDs.
- Paper: Seungjae Jeon's Master thesis [MS'07]
2. Verilog Translation Supporting Tool:
- FBD Verifier 1.0 [download] developed (2006.12) by Seungjae Jeon ('07 MS DSLab. in KAIST)
1. Automatic translation of synchronous Verilog from FBDs in POSCON pSET.
2. Automatic Execution of SMV model checking
3. Visualization of SMV model checking result
- Paper: [Preparing JSS submission]